培訓(xùn)方式以講課和實驗穿插進(jìn)行

 

Course Description

This is an Engineer Explorer series course. The Engineer Explorer courses explore advanced topics.

This course explores Incisive? comprehensive coverage features, with which you can measure how thoroughly your testbench exercises your design. The course addresses coverage of SystemC, VHDL, Verilog?, and mixed-language designs. Not all coverage features are available with all languages.

The course discusses the collection and analysis of the following types of coverage:

Code (block, expression, toggle, state, and arc) coverage
Data-oriented functional coverage using SystemVerilog covergroups
Control-oriented functional coverage using PSL and SystemVerilog assertions
Learning Objectives

After completing this course you will be able to:

Effectively use the Incisive comprehensive coverage with your SystemC, VHDL, Verilog, and mixed-language designs